A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a substrate; a gate line positioned on the substrate; a gate insulating layer positioned on the gate line; a semiconductor layer positioned on the gate insulating layer and having a channel portion; a data line including a source electrode and a drain electrode, the source and drain electrodes both positioned on the semiconductor layer; a passivation layer positioned on the data line and the drain electrode and having a contact hole formed therein; and a pixel electrode positioned on the passivation layer, wherein the pixel electrode contacts the drain electrode within the contact hole, and the channel portion of the semiconductor layer and the contact hole both overlap the gate line in a plan view of the substrate.