A display device and method are provided. The display device includes a timing controller configured to insert a clock between data and transmit the data in which the clock has been inserted, transmission lines configured to transfer the data in which the clock has been inserted, and data driver integrated circuits (ICs) configured to receive the data in which the clock has been inserted, separate the clock from the data, and drive data lines of a liquid crystal panel on the basis of the clock and the data. The timing controller includes a phase-locked loop (PLL) including an oscillator and an inductor-capacitor (LC) resonant circuit, and a reset signal generator configured to generate a reset signal causing the PLL to start coarse frequency tuning when initial power is applied or a frequency of an applied input clock changes.