发明授权
US09147500B2 Semiconductor memory device having resistive memory cells and method of testing the same
有权
具有电阻式存储单元的半导体存储器件及其测试方法
- 专利标题: Semiconductor memory device having resistive memory cells and method of testing the same
- 专利标题(中): 具有电阻式存储单元的半导体存储器件及其测试方法
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申请号: US13945007申请日: 2013-07-18
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公开(公告)号: US09147500B2公开(公告)日: 2015-09-29
- 发明人: Hye-Jin Kim , Hyung-Rok Oh , Dong-Seok Kang , Dong-Hyun Sohn , Sang-Beom Kang , Chul-Woo Park , Yun-Sang Lee
- 申请人: Samsung Electronics Co., Ltd.
- 申请人地址: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do
- 代理机构: Muir Patent Law, PLLC
- 优先权: KR10-2012-0078033 20120718
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C29/10 ; G11C11/16 ; G11C29/32 ; G11C29/34 ; G11C29/26
摘要:
A semiconductor memory device includes a memory cell array, a mode register set and a test circuit. The memory cell array includes a plurality of wordlines, a plurality of bitlines, and a plurality of spin-transfer torque magneto-resistive random access memory (STT-MRAM) cells, and each STT-MRAM cell disposed in a cross area of each wordline and bitline, and the STT-MRAM cell includes a magnetic tunnel junction (MTJ) element and a cell transistor. A gate of the cell transistor is coupled to a wordline, a first electrode of the cell transistor is coupled to a bitline via the MTJ element, and a second electrode of the cell transistor is coupled to a source line. The mode register set is configured to set a test mode, and the test circuit is configured to perform a test operation by using the mode register set.