Invention Grant
US09148298B2 Asymmetric ring topology for reduced latency in on-chip ring networks
有权
不对称环形拓扑，用于降低片上环形网络的延迟
- Patent Title: Asymmetric ring topology for reduced latency in on-chip ring networks
- Patent Title (中): 不对称环形拓扑，用于降低片上环形网络的延迟
-
Application No.: US13285733Application Date: 2011-10-31
-
Publication No.: US09148298B2Publication Date: 2015-09-29
- Inventor: Rohit Sunkam Ramanujam , Sailesh Kumar , William Lynch
- Applicant: Rohit Sunkam Ramanujam , Sailesh Kumar , William Lynch
- Applicant Address: US TX Plano
- Assignee: Futurewei Technologies, Inc.
- Current Assignee: Futurewei Technologies, Inc.
- Current Assignee Address: US TX Plano
- Agency: Conley Rose, P.C.
- Agent Grant Rodolph; Wiliam H. Dietrich
- Main IPC: H04L12/28
- IPC: H04L12/28 ; H04L12/42 ; G06F15/78 ; H04L12/40 ; H04J1/16
Abstract:
An apparatus comprising a chip comprising a plurality of nodes, a first plurality of links connecting the plurality of nodes in a first ring network having a first topology, and a second plurality of links connecting the plurality of nodes in a second ring network having a second topology, wherein the first topology is different than the second topology.
Public/Granted literature
- US20120201171A1 Asymmetric ring topology for reduced latency in on-chip ring networks Public/Granted day:2012-08-09
Information query
