Invention Grant
- Patent Title: System and method for critical path replication
- Patent Title (中): 关键路径复制的系统和方法
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Application No.: US13715721Application Date: 2012-12-14
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Publication No.: US09160336B2Publication Date: 2015-10-13
- Inventor: Abhishek Jain , Chittoor Parthasarathy , Kallol Chatterjee
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Amsterdam
- Assignee: STMICROELECTRONICS PVT LTD
- Current Assignee: STMICROELECTRONICS PVT LTD
- Current Assignee Address: NL Amsterdam
- Agency: Slater & Matsil, L.L.P.
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H03K19/003

Abstract:
Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.
Public/Granted literature
- US20140167812A1 System and Method for Critical Path Replication Public/Granted day:2014-06-19
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