Invention Grant
US09171755B2 Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction
有权
制造半导体器件的方法，其包括封装金属图案，其间具有用于寄生电容降低的气隙
- Patent Title: Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction
- Patent Title (中): 制造半导体器件的方法，其包括封装金属图案，其间具有用于寄生电容降低的气隙
-
Application No.: US14453310Application Date: 2014-08-06
-
Publication No.: US09171755B2Publication Date: 2015-10-27
- Inventor: Euibok Lee , Jongmin Baek , Dohyoung Kim , Tsukasa Matsuda , Youngwoo Cho , Jongseo Hong
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Gyeonggi-Do
- Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee: SAMSUNG ELECTRONICS CO., LTD.
- Current Assignee Address: KR Gyeonggi-Do
- Agency: Harness, Dickey & Pierce, PLC
- Priority: KR10-2013-0129376 20131029
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L21/764 ; H01L21/762
Abstract:
A method of manufacturing a semiconductor device may include: forming an interlayer insulating layer having openings on a substrate; forming a metal layer in the openings and on the interlayer insulating layer, the metal layer including a sidewall portion on a sidewall of each of the openings and a bottom portion on a bottom surface of each of the openings, wherein the bottom portion is thicker than the sidewall portion; reflowing the metal layer to form metal patterns in the openings, the metal patterns having top surfaces at a level lower than a topmost surface of the interlayer insulating layer; and/or forming capping patterns covering the metal patterns in the openings.
Public/Granted literature
- US20150115398A1 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME Public/Granted day:2015-04-30
Information query
IPC分类:
