Invention Grant
- Patent Title: High density substrate routing in BBUL package
- Patent Title (中): 高密度基板路由在BBUL封装
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Application No.: US14663689Application Date: 2015-03-20
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Publication No.: US09171816B2Publication Date: 2015-10-27
- Inventor: Weng Hong Teh , Chia-Pin Chiu
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L23/34
- IPC: H01L23/34 ; H01L23/00 ; H01L23/31 ; H01L25/16

Abstract:
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more embodiments a device can include a bumpless buildup layer (BBUL) substrate including a first die at least partially embedded in the BBUL substrate, the first die including a first plurality of high density interconnect pads. A second die can be at least partially embedded in the BBUL substrate, the second die including a second plurality of high density interconnect pads. A high density interconnect element can be embedded in the BBUL substrate, the high density interconnect element including a third plurality of high density interconnect pads electrically coupled to the first and second plurality of high density interconnect pads.
Public/Granted literature
- US20150194406A1 HIGH DENSITY SUBSTRATE ROUTING IN BBUL PACKAGE Public/Granted day:2015-07-09
Information query
IPC分类: