Invention Grant
- Patent Title: Semiconductor structures comprising a plurality of active areas separated by isolation regions
- Patent Title (中): 半导体结构包括由隔离区隔开的多个有效区域
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Application No.: US14541427Application Date: 2014-11-14
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Publication No.: US09171902B2Publication Date: 2015-10-27
- Inventor: Kunal R. Parekh , John K. Zahurak
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John, P.S.
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L29/06 ; H01L21/28 ; H01L21/308 ; H01L27/02 ; H01L27/108 ; H01L27/088 ; H01L29/423 ; H01L29/66
Abstract:
Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.
Public/Granted literature
- US20150069505A1 Semiconductor Structures Public/Granted day:2015-03-12
Information query
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