A display panel includes a gate line, a gate electrode, a planarization layer, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode, and a pixel electrode. The gate electrode extends from the gate line. The planarization layer covers the gate line and the gate electrode to have an opening exposing a portion of the gate electrode formed therethrough. The gate insulation layer covers a portion of the gate electrode exposed by the opening and the planarization layer. The active layer is formed on the gate insulation layer and corresponds to the gate electrode. The data line is formed. The source electrode extends from the data line to cover a portion of the opening. The drain electrode is spaced apart from the source electrode and covers a portion of the opening. The pixel electrode is connected to the drain electrode.