A power line communication (PLC) device comprises a processor and a memory coupled to the processor. The memory is configured to store program instructions executable by the processor to cause the PLC device perform operations. One or more time slots are sequentially scan in each of a plurality of frequency bands. A packet transmitted by a second PLC device to the PLC device over one of the plurality of frequency bands is detected. Additional packets received from the second PLC device across the plurality of frequency bands based, at least in part, upon the detected packet are synchronized. The additional packets are organized in a plurality of frames, each of the plurality of frames having been transmitted by the second PLC device to the PLC device over a respective one of the plurality of frequency bands. Each frame has a plurality of time slots, and each time slot has a pair of beacon and bandscan packets, Each bandscan packet includes information indicating a frequency band distinct from any of the plurality of different frequency bands to be used by the second PLC device to communicate with the first PLC device in a direction from the second PLC device to the first PLC device.