Invention Grant
US09177858B1 Methods for fabricating integrated circuits including barrier layers for interconnect structures
有权
用于制造包括用于互连结构的阻挡层的集成电路的方法
- Patent Title: Methods for fabricating integrated circuits including barrier layers for interconnect structures
- Patent Title (中): 用于制造包括用于互连结构的阻挡层的集成电路的方法
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Application No.: US14272787Application Date: 2014-05-08
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Publication No.: US09177858B1Publication Date: 2015-11-03
- Inventor: Xunyuan Zhang , Tibor Bolom , Kun Ho Ahn , Bernd Hintze , Frank Koschinsky
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/4763
- IPC: H01L21/4763 ; H01L21/768 ; H01L21/285
Abstract:
Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.
Public/Granted literature
- US20150325467A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS INCLUDING BARRIER LAYERS FOR INTERCONNECT STRUCTURES Public/Granted day:2015-11-12
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