Invention Grant
- Patent Title: Electrostatic protection for stacked multi-chip integrated circuits
- Patent Title (中): 堆叠多芯片集成电路的静电保护
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Application No.: US13646109Application Date: 2012-10-05
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Publication No.: US09184130B2Publication Date: 2015-11-10
- Inventor: Brian M. Henderson , Chiew-Guan Tan , Gregory A. Uvieghara , Reza Jalilizeinali
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Michelle S. Gallardo
- Main IPC: H02H9/00
- IPC: H02H9/00 ; H01L23/525 ; H01L23/60 ; H01L25/065 ; H01L25/00 ; H01L23/31 ; H01L23/48

Abstract:
One feature pertains to a multi-chip module that comprises at least a first integrated circuit (IC) die and a second IC die. The second IC die has an input/output (I/O) node electrically coupled to the first IC die by a through substrate via. The second die's active surface also includes a fuse that is electrically coupled to the I/O node and adapted to protect the second IC die from damage caused by an electrostatic discharge (ESD). In particular, the fuse protects the second IC die from ESD that may be generated as a result of electrically coupling the first die to the second die during the manufacturing of the multi-chip module. Upon coupling the first die to the second die, the fuse may bypass the ESD current generated by the ESD to ground. After packaging of the multi-chip module is complete, the fuse may be blown open.
Public/Granted literature
- US20140098448A1 ELECTROSTATIC PROTECTION FOR STACKED MULTI-CHIP INTEGRATED CIRCUITS Public/Granted day:2014-04-10
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