Invention Grant
US09184260B2 Methods for fabricating integrated circuits with robust gate electrode structure protection
有权
用于制造具有鲁棒栅极电极结构保护的集成电路的方法
- Patent Title: Methods for fabricating integrated circuits with robust gate electrode structure protection
- Patent Title (中): 用于制造具有鲁棒栅极电极结构保护的集成电路的方法
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Application No.: US14080558Application Date: 2013-11-14
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Publication No.: US09184260B2Publication Date: 2015-11-10
- Inventor: Joanna Wasyluk , Dominic Thurmer , Ardechir Pakfar , Markus Lenski
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L21/425
- IPC: H01L21/425 ; H01L21/8238 ; H01L21/336 ; H01L29/66 ; H01L29/51 ; H01L29/165

Abstract:
Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.
Public/Granted literature
- US20150132914A1 METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION Public/Granted day:2015-05-14
Information query
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