Invention Grant
US09184295B2 Method for manufacturing a suspended membrane and dual-gate MOS transistor
有权
制造悬浮膜和双栅极MOS晶体管的方法
- Patent Title: Method for manufacturing a suspended membrane and dual-gate MOS transistor
- Patent Title (中): 制造悬浮膜和双栅极MOS晶体管的方法
-
Application No.: US14077724Application Date: 2013-11-12
-
Publication No.: US09184295B2Publication Date: 2015-11-10
- Inventor: Stéphane Monfray , Thomas Skotnicki
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Seed IP Law Group PLLC
- Priority: FR0958280 20091123
- Main IPC: H01L29/786
- IPC: H01L29/786

Abstract:
A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
Public/Granted literature
- US20140070317A1 METHOD FOR MANUFACTURING A SUSPENDED MEMBRANE AND DUAL-GATE MOS TRANSISTOR Public/Granted day:2014-03-13
Information query
IPC分类: