Invention Grant
US09189328B2 Memory controller and method of operating the same 有权
内存控制器及其操作方法

Memory controller and method of operating the same
Abstract:
A memory controller includes a register configured to store a parity check matrix, and an error correcting code (ECC) decoder configured to perform error bit correction on data supplied from a non-volatile memory device using the parity check matrix. The parity check matrix includes N column matrices, where N is a natural number. Each of the N column matrices includes multiple sub-matrices, and a last sub-matrix of the multiple sub-matrices of each column matrix, which is a non-zero valued matrix that comes last in an decoding sequence of the ECC decoder, is an identity matrix.
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