Invention Grant
- Patent Title: Process for treating a semiconductor-on-insulator structure for improving thickness uniformity of the semiconductor layer
- Patent Title (中): 用于处理绝缘体上半导体结构以改善半导体层的厚度均匀性的方法
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Application No.: US14397287Application Date: 2013-05-01
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Publication No.: US09190284B2Publication Date: 2015-11-17
- Inventor: Walter Schwarzenbach , Carine Duret , Francois Boedt
- Applicant: Soitec
- Applicant Address: FR Bernin
- Assignee: SOITEC
- Current Assignee: SOITEC
- Current Assignee Address: FR Bernin
- Agency: TraskBritt
- Priority: FR1254841 20120525
- International Application: PCT/IB2013/000857 WO 20130501
- International Announcement: WO2013/175278 WO 20131128
- Main IPC: H01L21/306
- IPC: H01L21/306 ; H01L21/66 ; H01L21/762

Abstract:
The invention relates to a process for treating a structure of semiconductor-on-insulator type successively comprising a support substrate, a dielectric layer and a semiconductor layer having a thickness of less than or equal to 100 nm, the semiconductor layer being covered with a sacrificial oxide layer, comprising measuring, at a plurality of points distributed over the surface of the structure, the thickness of the sacrificial oxide layer and of the semiconductor layer, so as to produce a mapping of the thickness of the semiconductor layer and to determine, from the measurements, the average thickness of the semiconductor layer, selective etching of the sacrificial oxide layer so as to expose the semiconductor layer, and carrying out a chemical etching of the semiconductor layer, the application, temperature and/or duration conditions of which are adjusted as a function of the mapping and/or of the mean thickness of the semiconductor layer, so as to thin, at least locally, the semiconductor layer by a thickness identified as being an overthickness at the end of the measurement step.
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