发明授权
US09190346B2 Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
有权
通过3D集成电路的衬底背带实现锁定抑制和衬底噪声耦合减少
- 专利标题： Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
- 专利标题（中）： 通过3D集成电路的衬底背带实现锁定抑制和衬底噪声耦合减少
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申请号： US13601394申请日： 2012-08-31
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公开(公告)号： US09190346B2公开(公告)日： 2015-11-17
- 发明人: Victor Moroz , Jamil Kawa
- 申请人： Victor Moroz , Jamil Kawa
- 申请人地址： US CA Mountain View
- 专利权人： SYNOPSYS, INC.
- 当前专利权人： SYNOPSYS, INC.
- 当前专利权人地址： US CA Mountain View
- 代理机构： Haynes Beffel & Wolfeld LLP
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H01L23/48 ; H01L21/768 ; H01L23/00
摘要：
Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.
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