Multi chip package, manufacturing method thereof, and memory system having the multi chip package
Abstract:
A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.
Information query
Patent Agency Ranking
0/0