Invention Grant
- Patent Title: Methods and apparatus for congestion-aware buffering using voltage isolation pathways for integrated circuit designs with multi-power domains
- Patent Title (中): 使用多电源域的集成电路设计的电压隔离通道的拥塞感知缓冲的方法和装置
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Application No.: US14484904Application Date: 2014-09-12
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Publication No.: US09190358B2Publication Date: 2015-11-17
- Inventor: Sundararajan Ranganathan , Paras Gupta , Raghavendra Dasegowda , Rajesh Verma , Parissa Najdesamii
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Haynes and Boone, LLP
- Main IPC: H01L29/00
- IPC: H01L29/00 ; H01L21/82 ; H01L23/538 ; G06F17/50 ; H01L29/06 ; H01L27/02
Abstract:
A semiconductor apparatus is provided herein for buffering of nets routed through one or more areas associated with a first power domain that is different from a second power domain associated with the buffers and the buffered nets by limiting placement of these buffers in patterned areas associated with the second power domain. This provides for the routing of the buffered nets to be determined not only based on the shortest distance to travel from Point A to Point B, but also takes into account routing congestion on the semiconductor apparatus. Consequently, if an area on the semiconductor apparatus is congested, the buffered nets may be routed around the congestion. As such, although a path taken by a particular signal through the integrated circuit is not a direct route, it may still be of a distance to support a speed at which the particular signal needs to be transferred.
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