Invention Grant
- Patent Title: Array substrate and method for fabricating the same
- Patent Title (中): 阵列基板及其制造方法
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Application No.: US13995122Application Date: 2012-11-07
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Publication No.: US09190564B2Publication Date: 2015-11-17
- Inventor: Jing Yang , Jianshe Xue , Xiang Liu
- Applicant: BOE Technology Group Co., Ltd.
- Applicant Address: CN Beijing
- Assignee: BOE Technology Group Co., Ltd.
- Current Assignee: BOE Technology Group Co., Ltd.
- Current Assignee Address: CN Beijing
- Priority: CN201210065761 20120313
- International Application: PCT/CN2012/084187 WO 20121107
- International Announcement: WO2013/135062 WO 20130919
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L33/08 ; G02F1/1362 ; H01L27/12

Abstract:
An array substrate and a method for fabricating the same are disclosed. The method for fabricating the array substrate comprises: forming a pattern of a gate electrode (2) and a common electrode (3) on a substrate (1); forming a pattern of a gate insulating layer (4), an active layer (5), a source/drain electrode layer (6) and a first passivation layer (7), wherein the first passivation layer (7) has a via hole and a thin film transistor (TFT) channel window, and the TFT channel window is located above the gate electrode (2); forming a TFT channel and a pixel electrode (9) with slits, wherein the pixel electrode (9) is connected to one of the source/drain electrode (6) through the via hole. The method is not only simple and stable but also improves the TFT quality.
Public/Granted literature
- US20140070239A1 Array Substrate And Method For Fabricating The Same Public/Granted day:2014-03-13
Information query
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