发明授权
- 专利标题: Circuit and method for calculating error of sampling clock, and signal receiving circuit and method
- 专利标题(中): 采样时钟误差的电路及方法,信号接收电路及方法
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申请号: US14535599申请日: 2014-11-07
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公开(公告)号: US09191195B2公开(公告)日: 2015-11-17
- 发明人: Chih-Cheng Kuo , Wen-Chieh Yang , Chu-Hsin Chang , Tai-Lai Tung
- 申请人: MStar Semiconductor, Inc.
- 申请人地址: TW Hsinchu Hsien
- 专利权人: MSTAR SEMICONDUCTOR, INC.
- 当前专利权人: MSTAR SEMICONDUCTOR, INC.
- 当前专利权人地址: TW Hsinchu Hsien
- 代理机构: WPAT, PC
- 代理商 Justin King
- 优先权: TW102140540A 20131107
- 主分类号: H04L7/04
- IPC分类号: H04L7/04 ; H04L25/03 ; H04N21/438
摘要:
A method for calculating an error of a sampling clock is provided. The sampling clock is used for sampling a signal to generate a first sample data group and a second sample data group. Each of the first and second sample data groups includes a header having a predetermined sequence. The method includes: performing a correlation operation on the first and second sample data groups with data of the predetermined format to obtain first and second correlation results, respectively; comparing the first and second correlation results to generate a sample data group offset; and generating the error of the sampling clock according to the sample data group offset and a time difference between the first and second sample data groups.
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