Invention Grant
- Patent Title: Common shared memory in a verification system
- Patent Title (中): 验证系统中的共享共享内存
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Application No.: US13078786Application Date: 2011-04-01
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Publication No.: US09195784B2Publication Date: 2015-11-24
- Inventor: Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
- Applicant: Ping-Sheng Tseng , Sharon Sheau-Pyng Lin , Quincy Kun-Hsu Shen , Mike Mon Yen Tsai , Steven Wang
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger, Esq.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
Public/Granted literature
- US20110307233A1 COMMON SHARED MEMORY IN A VERIFICATION SYSTEM Public/Granted day:2011-12-15
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