Invention Grant
- Patent Title: Semiconductor package with single sided substrate design and manufacturing methods thereof
- Patent Title (中): 具有单面基板的半导体封装及其制造方法
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Application No.: US14453139Application Date: 2014-08-06
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Publication No.: US09196597B2Publication Date: 2015-11-24
- Inventor: Yuan-Chang Su , Shih-Fu Huang , Chia-Cheng Chen , Tzu-Hui Chen , Kuang-Hsiung Chen , Pao-Ming Hsieh , Ming Chiang Lee , Bernd Karl Appelt
- Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Applicant Address: TW Kaohsiung
- Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
- Current Assignee Address: TW Kaohsiung
- Agency: Foley & Lardner LLP
- Agent Cliff Z. Liu; Angela D. Murch
- Priority: TW99112317A 20100420
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L23/00 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/29 ; H01L23/31 ; H01L23/498 ; H01L23/522 ; H01L23/28

Abstract:
A multilayer substrate includes a first outer conductive patterned layer, a first insulating layer exposing a portion of the first outer conductive patterned layer to define a first set of pads, a second outer conductive patterned layer, and a second insulating layer exposing a portion of the second outer conductive patterned layer to define a second set of pads. The multilayer substrate further includes inner layers each with an inner conductive patterned layer, multiple inner conductive posts formed adjacent to the inner conductive patterned layer, and an inner dielectric layer, where the inner conductive patterned layer and the inner conductive posts are embedded in the inner dielectric layer, and a top surface of each of the inner conductive posts is exposed from the inner dielectric layer.
Public/Granted literature
- US20140346670A1 SEMICONDUCTOR PACKAGE WITH SINGLE SIDED SUBSTRATE DESIGN AND MANUFACTURING METHODS THEREOF Public/Granted day:2014-11-27
Information query
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