Invention Grant
- Patent Title: Stress release layout and associated methods and devices
- Patent Title (中): 压力释放布局及相关方法和装置
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Application No.: US13708625Application Date: 2012-12-07
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Publication No.: US09196642B2Publication Date: 2015-11-24
- Inventor: Tsung-Han Tsai , Allen Tseng , Yen-Hsung Ho , Chun-Hao Chou , Kuo-Cheng Lee , Volume Chien , Chi-Cherng Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L27/146
- IPC: H01L27/146 ; H01L21/00 ; H01L31/18

Abstract:
An embodiment semiconductor device includes a substrate such as a silicon or silicon-containing film, a pixel array supported by the substrate, and a metal stress release feature arranged around a periphery of the pixel array. The metal stress release feature may be formed from metal strips or discrete metal elements. The metal stress release feature may be arranged in a stress release pattern that uses a single line or a plurality of lines. The metal stress release pattern may also use metal corner elements at ends of the lines.
Public/Granted literature
- US20140070352A1 Stress Release Layout and Associated Methods and Devices Public/Granted day:2014-03-13
Information query
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