Invention Grant
- Patent Title: Memory device with variable code rate
- Patent Title (中): 具有可变代码率的存储器件
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Application No.: US14025327Application Date: 2013-09-12
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Publication No.: US09201728B2Publication Date: 2015-12-01
- Inventor: Ara Patapoutian , Ryan James Goss , Mark Allen Gaertner , Bruce Douglas Buch , Arvind Sridharan
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Hall Estill Attorneys at Law
- Main IPC: G06F11/10
- IPC: G06F11/10

Abstract:
Method and apparatus for managing data in a memory, such as a flash memory. In accordance with some embodiments, the apparatus has a solid-state non-volatile memory and a processing circuit configured to write data to a selected location of the memory. The data are arranged in the form of multi-bit code words each comprising a user data payload and associated parity data configured to correct one or more bit errors in the user data payload. The processing circuit adjusts at least a selected one of a size of the code words, a size of the user data payloads or a size of the parity data responsive to at least a selected one of an accumulated count of access operations upon the selected location or an error rate associated with the selected location.
Public/Granted literature
- US20150074487A1 Memory Device with Variable Code Rate Public/Granted day:2015-03-12
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