Invention Grant
US09202871B2 JFET devices with increased barrier height and methods of making same
有权
具有增加势垒高度的JFET器件及其制造方法
- Patent Title: JFET devices with increased barrier height and methods of making same
- Patent Title (中): 具有增加势垒高度的JFET器件及其制造方法
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Application No.: US14275847Application Date: 2014-05-12
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Publication No.: US09202871B2Publication Date: 2015-12-01
- Inventor: Chandra Mouli
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Fletcher Yoder, P.C.
- Main IPC: H01L29/16
- IPC: H01L29/16 ; H01L27/098 ; H01L29/267 ; H01L29/66 ; H01L29/808 ; H01L29/812
Abstract:
Devices for providing transistors with improved operating characteristics are provided. In one example, a system includes a processor and a memory device. A transistor of the processor or the memory device includes a channel in a semiconductor substrate that is undoped or intrinsic. A metal gate is disposed directly on top of the channel, and the bandgap of the semiconductor substrate and the work function of the metal form a Schottky barrier.
Public/Granted literature
- US20140246680A1 JFET Devices with Increased Barrier Height and Methods of Making Same Public/Granted day:2014-09-04
Information query
IPC分类:
