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发明授权
US09208899B2 Universal test structures based SRAM on-chip parametric test module and methods of operating and testing 有权
基于通用测试结构的SRAM片上参数测试模块和操作和测试方法

Universal test structures based SRAM on-chip parametric test module and methods of operating and testing
摘要：
An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.
摘要（中）：

集成电路片上参数（OCP）测试结构包括具有UTS端口的静态随机存取存储器（SRAM）通用测试结构（UTS），以及被配置为确定SRAM UTS的第一和第二UTS端口以独立连接到 第一和第二片上测试焊盘。 集成电路OCP测试结构还包括连接到OCP控制器并被配置为将SRAM UTS的第一和第二UTS端口分别连接到第一和第二片上测试焊盘的UTS OCP路由器。 还包括操作集成电路OCP测试结构和集成电路的OCP测试的方法。

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