Invention Grant
US09209110B2 Integrated device comprising wires as vias in an encapsulation layer
有权
集成器件，其包括导线作为封装层中的通孔
- Patent Title: Integrated device comprising wires as vias in an encapsulation layer
- Patent Title (中): 集成器件，其包括导线作为封装层中的通孔
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Application No.: US14272494Application Date: 2014-05-07
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Publication No.: US09209110B2Publication Date: 2015-12-08
- Inventor: Reynante Tamunan Alvarado , Lizabeth Ann Keser , Steve Joseph Bezuk
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP
- Main IPC: H01L23/04
- IPC: H01L23/04 ; H01L23/48 ; H01L21/768 ; H01L25/065 ; H01L25/00 ; H01L21/56 ; H01L23/31
Abstract:
Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.
Public/Granted literature
- US20150325496A1 INTEGRATED DEVICE COMPRISING WIRES AS VIAS IN AN ENCAPSULATION LAYER Public/Granted day:2015-11-12
Information query
IPC分类:
