Invention Grant
US09209806B2 Delay circuit independent of supply voltage 有权
延迟电路独立于电源电压

Delay circuit independent of supply voltage
Abstract:
A delay circuit in which the delay is independent of variations in the power supply which powers the logic gates of the delay circuit is disclosed. By separating the CMOS transistors that form each logic gate by additional CMOS bias transistors which are biased at a controlled voltage, variations in the gate delay of the inverter transistors due to variations in the power supply voltage for the inverter transistors may be minimized. In one embodiment, the constant bias voltage may be provided by a constant current source comprising a series of amplifiers each having a gain significantly less than one connected to a triple cascode.
Public/Granted literature
Information query
Patent Agency Ranking
0/0