Invention Grant
US09213358B2 Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components
有权
单片三维(3D)集成电路(IC)(3DIC)跨层时钟偏移管理系统,方法及相关组件
- Patent Title: Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems, methods and related components
- Patent Title (中): 单片三维(3D)集成电路(IC)(3DIC)跨层时钟偏移管理系统,方法及相关组件
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Application No.: US14159028Application Date: 2014-01-20
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Publication No.: US09213358B2Publication Date: 2015-12-15
- Inventor: Pratyush Kamal , Yang Du
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Withrow & Terranova, PLLC
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F1/10 ; H01L27/06

Abstract:
Monolithic three dimensional (3D) integrated circuit (IC) (3DIC) cross-tier clock skew management systems are disclosed. Methods and related components are also disclosed. In an exemplary embodiment, to offset the skew that may result across the tiers in the clock tree, a cross-tier clock balancing scheme makes use of automatic delay adjustment. In particular, a delay sensing circuit detects a difference in delay at comparable points in the clock tree between different tiers and instructs a programmable delay element to delay the clock signals on the faster of the two tiers. In a second exemplary embodiment, a metal mesh is provided to all elements within the clock tree and acts as a signal aggregator that provides clock signals to the clocked elements substantially simultaneously.
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