Invention Grant
- Patent Title: Flash translation layer with lower write amplification
- Patent Title (中): Flash转换层具有较低的写入放大率
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Application No.: US13889521Application Date: 2013-05-08
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Publication No.: US09213633B2Publication Date: 2015-12-15
- Inventor: Timothy L. Canepa , Earl T. Cohen , Alex G. Tang
- Applicant: Seagate Technology LLC
- Applicant Address: US CA Cupertino
- Assignee: Seagate Technology LLC
- Current Assignee: Seagate Technology LLC
- Current Assignee Address: US CA Cupertino
- Agency: Christopher P. Maiorana, PC
- Main IPC: G06F12/02
- IPC: G06F12/02

Abstract:
A method of associating a logical block address with a physical location in a non-volatile memory includes (A) in response to a write request comprising a respective logical block address in a logical block address space and respective data to be written to the non-volatile memory, determining a physical location in the non-volatile memory to store the respective data of the write request, (B) adding an entry to a journal, such that the added entry trails any entries already in the journal and the added entry has a respective logical block address field set to the respective logical block address of the write request and a respective physical location field set to the determined physical location, and (C) updating one of a plurality of second-level map pages in a two-level map according to the respective logical block address of the write request with the determined physical location.
Public/Granted literature
- US20140325117A1 FLASH TRANSLATION LAYER WITH LOWER WRITE AMPLIFICATION Public/Granted day:2014-10-30
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