Invention Grant
US09218289B2 Multi-core compute cache coherency with a release consistency memory ordering model
有权
具有发布一致性内存排序模型的多核计算高速缓存一致性
- Patent Title: Multi-core compute cache coherency with a release consistency memory ordering model
- Patent Title (中): 具有发布一致性内存排序模型的多核计算高速缓存一致性
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Application No.: US13958399Application Date: 2013-08-02
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Publication No.: US09218289B2Publication Date: 2015-12-22
- Inventor: Bohuslav Rychlik , Tzung Ren Tzeng , Andrew Evan Gruber , Alexei V. Bourd , Colin Christopher Sharp , Eric Demers
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Shumaker & Sieffert, P.A.
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F12/08 ; G06F13/00 ; G06F13/28
Abstract:
A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.
Public/Granted literature
- US20140040552A1 MULTI-CORE COMPUTE CACHE COHERENCY WITH A RELEASE CONSISTENCY MEMORY ORDERING MODEL Public/Granted day:2014-02-06
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