A display device includes a display panel including gate lines, data lines, and pixels each connected to a corresponding gate line and a corresponding data line, a gate driver configured to drive the gate lines, a data driver configured to drive the data lines, and a timing controller configured to generate control signals to control the data driver and to apply a vertical synchronization start signal including a first pulse, a second pulse, a first gate pulse signal, and a second gate pulse signal to the gate driver. The gate driver applies gate driving signals to the gate lines to pre-charge the pixels in response to the first pulse of the vertical synchronization start signal and the first gate pulse signal, and to main-charge the pixels in response to the second pulse of the vertical synchronization start signal and the second gate pulse signal.