Invention Grant
- Patent Title: Capless on chip voltage regulator using adaptive bulk bias
- Patent Title (中): 无限片上稳压器采用自适应体积偏置
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Application No.: US14788682Application Date: 2015-06-30
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Publication No.: US09229462B2Publication Date: 2016-01-05
- Inventor: Hemant Shukla , Saurabh Kumar Singh , Nitin Bansal
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMicroelectronics International N.V.
- Current Assignee: STMicroelectronics International N.V.
- Current Assignee Address: NL Schiphol
- Agency: Seed IP Law Group PLLC
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F1/46

Abstract:
An FDSOI integrated circuit die supplies on an output node a regulated output voltage based on a reference voltage. A pass transistor that passes a first current to the output node. A feedback loop regulates the output voltage by generating a second current based on the first current and applying a control signal to the pass transistor based on the second current. A loop current adaptor adapts a ratio of the first and second currents by adjusting a back gate bias voltage applied to a back gate of loop transistor of the feedback loop.
Public/Granted literature
- US20150301540A1 CAPLESS ON CHIP VOLTAGE REGULATOR USING ADAPTIVE BULK BIAS Public/Granted day:2015-10-22
Information query
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