Invention Grant
- Patent Title: Method of fabricating wafer-level chip package
- Patent Title (中): 制造晶圆级芯片封装的方法
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Application No.: US14508989Application Date: 2014-10-07
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Publication No.: US09230927B2Publication Date: 2016-01-05
- Inventor: Chuan-Jin Shiu , Tsang-Yu Liu , Chih-Wei Ho , Shih-Hsing Chan , Ching-Jui Chuang
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Main IPC: H01L23/00
- IPC: H01L23/00

Abstract:
A method of fabricating a wafer-level chip package is provided. First, a wafer with two adjacent chips is provided, the wafer having an upper surface and a lower surface, and one side of each chip includes a conducting pad on the lower surface. A recess and an isolation layer extend from the upper surface to the lower surface, which the recess exposes the conducting pad. A part of the isolation layer is disposed in the recess with an opening to expose the conducting pad. A conductive layer is formed on the isolation layer and the conductive pad, and a photo-resist layer is spray coated on the conductive layer. The photo-resist layer is exposed and developed to expose the conductive layer, and the conductive layer is etched to form a redistribution layer. After stripping the photo-resist layer, a solder layer is formed on the isolation layer and the redistribution layer.
Public/Granted literature
- US20150099357A1 METHOD OF FABRICATING WAFER-LEVEL CHIP PACKAGE Public/Granted day:2015-04-09
Information query
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