Invention Grant
- Patent Title: Dynamic global memory bit line usage as storage node
- Patent Title (中): 动态全局内存位线用作存储节点
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Application No.: US14497566Application Date: 2014-09-26
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Publication No.: US09236100B1Publication Date: 2016-01-12
- Inventor: Greg M. Hess , Ramesh Arvapalli
- Applicant: Apple Inc.
- Applicant Address: US CA Cupertino
- Assignee: Apple Inc.
- Current Assignee: Apple Inc.
- Current Assignee Address: US CA Cupertino
- Agency: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.
- Main IPC: G11C7/10
- IPC: G11C7/10 ; G11C7/12 ; G11C7/22

Abstract:
An apparatus, system, and method are contemplated in which the apparatus may include a memory with a plurality of pages, circuitry, and a plurality of pre-charge circuits. The circuitry may be configured to receive a first read command and address, corresponding to a given page. The plurality of pre-charge circuits may be configured to charge a plurality of data lines to a predetermined voltage. The circuitry may be configured to read data values from the memory, and transfer the data values to the plurality of data lines. The plurality of pre-charge circuits may be configured to maintain the data on the plurality of data lines. The circuitry may select a first subset of the maintained data, receive a second read command and a second address by the memory, and select a second subset of the maintained data responsive to a determination that the second address corresponds to the given page.
Information query