发明授权
- 专利标题: Test access architecture for TSV-based 3D stacked ICS
- 专利标题(中): 基于TSV的3D堆叠ICS的测试访问架构
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申请号: US13626538申请日: 2012-09-25
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公开(公告)号: US09239359B2公开(公告)日: 2016-01-19
- 发明人: Erik Jan Marinissen , Jacobus Verbree , Mario Konijnenburg , Chun-Chuan Chi
- 申请人: IMEC , Stichting IMEC Nederland
- 申请人地址: BE Leuven NL Eindhoven
- 专利权人: IMEC,Stichting IMEC Nederland
- 当前专利权人: IMEC,Stichting IMEC Nederland
- 当前专利权人地址: BE Leuven NL Eindhoven
- 代理机构: Knobbe, Martens, Olson & Bear LLP
- 优先权: EP10177675 20100920
- 主分类号: G01R31/3185
- IPC分类号: G01R31/3185 ; G01R31/3177 ; G01R31/317
摘要:
A test access architecture is disclosed for 3D-SICs that allows for both pre-bond die testing and post-bond stack testing. The test access architecture is based on a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units to allow optimization of the 3D-SIC test flow. The architecture builds on and reuses existing design for test (DfT) hardware at the core, die, and product level. Test access is provided to an individual die stack via a test structure called a wrapper unit.
公开/授权文献
- US20130024737A1 TEST ACCESS ARCHITECTURE FOR TSV-BASED 3D STACKED ICS 公开/授权日:2013-01-24
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