Invention Grant
- Patent Title: Integrated circuits and methods of forming the same with multiple embedded interconnect connection to same through-semiconductor via
- Patent Title (中): 集成电路和与多个嵌入式互连连接形成相同通孔半导体通孔的方法
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Application No.: US13747579Application Date: 2013-01-23
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Publication No.: US09245790B2Publication Date: 2016-01-26
- Inventor: Sarasvathi Thangaraju , Chun Yu Wong
- Applicant: GLOBALFOUNDRIES, Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee: GLOBALFOUNDRIES, INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ingrassia Fisher & Lorenz, P.C.
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L21/768 ; H01L23/528

Abstract:
Integrated circuits, methods of forming integrated circuits, and methods of sensing voiding between a through-semiconductor via and a subsequent layer that overlies the through-semiconductor via in integrated circuits are provided. An exemplary method of forming an integrated circuit includes forming a plurality of semiconductor devices on a semiconductor substrate. A through-semiconductor via is formed in the semiconductor substrate, and an interlayer dielectric layer is formed that overlies the through-semiconductor via and the plurality of semiconductor devices. A first interconnect via is embedded within the interlayer dielectric layer, and a second interconnect via is embedded within the interlayer dielectric layer. The first interconnect via and the second interconnect via are in electrical communication with the through-semiconductor via at spaced locations from each other on the through-semiconductor via.
Public/Granted literature
Information query
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