High-speed data links between a processor and off-chip DRAM utilizes pulse-amplitude-modulation (PAM) signaling to increase data rate for a given bandwidth and resource budget in SoCs. However, the termination resistor used in the transmission line interface between processor and DRAM consumes large amounts of power during PAM signaling. By adding a biasing source between Ground and the termination resistor, the “floor voltage” that the termination resistor uses as a reference for determining signaling levels may be raised. Raising the floor voltage reduces the amount of voltage across the termination resistor and reduces power consumption accordingly. The biasing source is adjusted to various increments of the maximum amplitude of the PAM signaling. A floor voltage of one-half of the maximum amplitude of PAM signaling produces minimum power consumption in the receiver. Additionally, data inversion pre-coding may be concatenated with the floor voltage adjustment to further maximize power savings of the interface.