发明授权
US09257527B2 Nanowire transistor structures with merged source/drain regions using auxiliary pillars
有权
具有合并源极/漏极区域的纳米线晶体管结构使用辅助柱
- 专利标题： Nanowire transistor structures with merged source/drain regions using auxiliary pillars
- 专利标题（中）： 具有合并源极/漏极区域的纳米线晶体管结构使用辅助柱
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申请号： US14181564申请日： 2014-02-14
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公开(公告)号： US09257527B2公开(公告)日： 2016-02-09
- 发明人: Pouya Hashemi , Ali Khakifirooz , Alexander Reznicek
- 申请人： International Business Machines Corporation
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 代理机构： Otterstedt, Ellenbogen & Kammer, LLP
- 代理商 Louis J. Percello
- 主分类号： H01L29/775
- IPC分类号： H01L29/775 ; H01L29/66 ; H01L29/423 ; H01L21/02 ; H01L29/786 ; H01L29/06
摘要：
A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.
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