Invention Grant
- Patent Title: Layout boundary method
- Patent Title (中): 布局边界法
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Application No.: US13919037Application Date: 2013-06-17
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Publication No.: US09262570B2Publication Date: 2016-02-16
- Inventor: Chin-Hsiung Hsu , Wen-Hao Chen , Ho Che Yu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Associates, LLC
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.
Public/Granted literature
- US20140282344A1 LAYOUT BOUNDARY METHOD Public/Granted day:2014-09-18
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