发明授权
US09263103B2 Method and apparatus for calibrating write timing in a memory system
有权
用于校准存储器系统中的写入定时的方法和装置
- 专利标题: Method and apparatus for calibrating write timing in a memory system
- 专利标题(中): 用于校准存储器系统中的写入定时的方法和装置
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申请号: US12049928申请日: 2008-03-17
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公开(公告)号: US09263103B2公开(公告)日: 2016-02-16
- 发明人: Thomas J. Giovannini , Alok Gupta , Ian Shaeffer , Steven C. Woo
- 申请人: Thomas J. Giovannini , Alok Gupta , Ian Shaeffer , Steven C. Woo
- 申请人地址: US CA Sunnyvale
- 专利权人: Rambus Inc.
- 当前专利权人: Rambus Inc.
- 当前专利权人地址: US CA Sunnyvale
- 代理机构: Peninsula Patent Group
- 代理商 Lance M. Kreisman
- 主分类号: G06F12/00
- IPC分类号: G06F12/00 ; G11C11/4076 ; G06F3/06 ; G06F5/06 ; G06F1/08 ; G11C7/10 ; G06F13/16 ; G06F12/06 ; G11C11/409
摘要:
A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period. In a variation of this system, the phase detector on the memory chip is configured to receive signals including a clock signal, a marking signal and a data-strobe signal from the memory controller, wherein the marking signal includes a pulse which marks a specific clock cycle in the clock signal. In this variation, the phase detector is configured to use the marking signal to window the specific clock cycle in the clock signal, and to use the data-strobe signal to capture the windowed clock signal, thereby creating a feedback signal which is returned to the memory controller to facilitate calibration of the timing relationship.