Invention Grant
- Patent Title: Dopant etch selectivity control
- Patent Title (中): 掺杂剂蚀刻选择性控制
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Application No.: US14230590Application Date: 2014-03-31
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Publication No.: US09263278B2Publication Date: 2016-02-16
- Inventor: Vinod R. Purayath , Anchuan Wang , Nitin K. Ingle
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Kilpatrick Townsend & Stockton LLP
- Main IPC: H01L21/3065
- IPC: H01L21/3065 ; H01J37/00 ; H01L21/28 ; H01L21/3213 ; H01J37/32

Abstract:
Methods of etching two doped silicon portions at two different etch rates are described. An n-type silicon portion may be etched faster than a p-type silicon portion when both are exposed and present on the same substrate. The n-type silicon portion may be doped with phosphorus and the p-type silicon portion may be doped with boron. In one example, the n-type silicon portion is single crystal silicon and the p-type silicon portion is polycrystalline silicon (a.k.a. polysilicon). The p-type silicon portion may be a polysilicon floating gate in a flash memory cell and may be located above a gate silicon oxide which, in turn, is above an n-type active area single crystal silicon portion. The additional trimming of the n-type active area silicon portion may reduce the accumulation of trapped charges during use and increase the lifespan of flash memory devices.
Public/Granted literature
- US20150170920A1 DOPANT ETCH SELECTIVITY CONTROL Public/Granted day:2015-06-18
Information query
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