A controller includes a memory test logic circuit to detect a malfunctioning row of primary data storage elements within an external memory device, an internal memory to store an address corresponding to the malfunctioning row of the external memory device, and a memory setup logic circuit to initiate a repair mode in the external memory device and to end the repair mode in the external memory device. The controller further includes a port to couple to an address line to transmit the address corresponding to the malfunctioning row of the external memory device.