Invention Grant
- Patent Title: Insulation wall between transistors on SOI
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Application No.: US14605064Application Date: 2015-01-26
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Publication No.: US09269768B2Publication Date: 2016-02-23
- Inventor: David Barge , Pierre Morin
- Applicant: STMICROELECTRONICS (CROLLES 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee: STMICROELECTRONICS (CROLLES 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: FR1157596 20110829
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/762 ; H01L27/12

Abstract:
An insulation wall separating transistors formed in a thin semiconductor layer resting on an insulating layer laid on a semiconductor substrate, this wall being formed of an insulating material and comprising a wall crossing the thin layer and the insulating layer and penetrating into the substrate, and lateral extensions extending in the substrate under the insulating layer.
Public/Granted literature
- US20150137242A1 INSULATION WALL BETWEEN TRANSISTORS ON SOI Public/Granted day:2015-05-21
Information query
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