Invention Grant
- Patent Title: Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors
- Patent Title (中): 在低温下沉积氮化硅层,以防止栅介质再生长高K金属栅场效应晶体管
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Application No.: US14037423Application Date: 2013-09-26
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Publication No.: US09269786B2Publication Date: 2016-02-23
- Inventor: Anthony I-Chih Chou , Arvind Kumar , Shreesh Narasimha , Claude Ortolland , Kai Zhao
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee: GLOBALFOUNDRIES Inc.
- Current Assignee Address: KY Grand Cayman
- Agency: Heslin Rothenberg Farley & Mesiti P.C.
- Main IPC: H01L29/76
- IPC: H01L29/76 ; H01L29/51 ; H01L27/092 ; H01L21/8238

Abstract:
Standard High-K metal gate (HKMG) CMOS technologies fabricated using the replacement metal gate (RMG), also known as gate-last, integration flow, are susceptible to oxygen ingress into the high-K gate dielectric layer and oxygen diffusion into the gate dielectric and semiconductor channel region. The oxygen at the gate dielectric and semiconductor channel interface induces unwanted oxide regrowth that results in an effective oxide thickness increase, and transistor threshold voltage shifts, both of which are highly variable and degrade semiconductor chip performance. By introducing silicon nitride deposited at low temperature, after the metal gate formation, the oxygen ingress and gate dielectric regrowth can be avoided, and a high semiconductor chip performance is maintained.
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