Invention Grant
- Patent Title: Method of manufacturing a junction electronic device having a 2-dimensional material as a channel
- Patent Title (中): 制造具有2维材料作为通道的结电子器件的方法
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Application No.: US14258416Application Date: 2014-04-22
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Publication No.: US09275860B2Publication Date: 2016-03-01
- Inventor: Young Jun Yu , Jin Soo Kim , Hong Kyw Choi , Jin Sik Choi , Jin Tae Kim , Kwang Hyo Chung , Doo Hyeb Youn , Choon Gi Choi
- Applicant: Electronics and Telecommunications Research Institute
- Applicant Address: KR Daejeon
- Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Current Assignee Address: KR Daejeon
- Agency: Rabin & Berdo, P.C.
- Priority: KR10-2014-0014679 20140210
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/02 ; H01L29/778 ; H01L29/24

Abstract:
A method of manufacturing a junction electronic device having a 2-Dimensional (2D) material as a channel, includes forming a pattern portion by surface-treating a substrate so that the patterned portion has a higher surface potential than other portions of the substrate; bonding a 2D material to rthe patterned portion having the higher surface potential by spraying a liquid including 2D material flakes onto the substrate; forming a pair of first electrodes in contact with both ends of the 2D material disposed on the substrate; forming a dielectric layer on the first electrodes and the 2D material; and forming a second electrode on the dielectric layer. The 2D materials are disposed at desired positions by chemical exfoliation.
Public/Granted literature
- US20150228481A1 METHOD OF MANUFACTURING JUNCTION ELECTRONIC DEVICE BY USING 2- DIMENSIONAL MATERIAL Public/Granted day:2015-08-13
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