发明授权
- 专利标题: Vertical semiconductor devices including superlattice punch through stop layer and related methods
- 专利标题(中): 垂直半导体器件包括超晶格穿通止动层及相关方法
-
申请号: US14550244申请日: 2014-11-21
-
公开(公告)号: US09275996B2公开(公告)日: 2016-03-01
- 发明人: Robert Mears , Hideki Takeuchi , Erwin Trautmann
- 申请人: MEARS Technologies, Inc.
- 申请人地址: US MA Wellesley Hills
- 专利权人: MEARS TECHNOLOGIES, INC.
- 当前专利权人: MEARS TECHNOLOGIES, INC.
- 当前专利权人地址: US MA Wellesley Hills
- 代理机构: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- 主分类号: H01L21/336
- IPC分类号: H01L21/336 ; H01L27/088 ; H01L29/66 ; H01L29/78 ; H01L29/10 ; H01L21/324 ; H01L21/8234 ; H01L29/15 ; H01L29/165
摘要:
A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
公开/授权文献
信息查询
IPC分类: