Invention Grant
US09292295B2 Voltage droop reduction by delayed back-propagation of pipeline ready signal
有权
通过管道就绪信号的延迟反向传播降低电压
- Patent Title: Voltage droop reduction by delayed back-propagation of pipeline ready signal
- Patent Title (中): 通过管道就绪信号的延迟反向传播降低电压
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Application No.: US13914528Application Date: 2013-06-10
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Publication No.: US09292295B2Publication Date: 2016-03-22
- Inventor: Philip Payman Shirvani , Peter Benjamin Sommers , Eric T. Anderson
- Applicant: NVIDIA Corporation
- Applicant Address: US CA Santa Clara
- Assignee: NVIDIA Corporation
- Current Assignee: NVIDIA Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Zilka-Kotab, PC
- Main IPC: G06F1/04
- IPC: G06F1/04 ; G06F9/38
Abstract:
A system, method, and computer program product for generating flow-control signals for a processing pipeline is disclosed. The method includes the steps of generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal received from a second pipeline stage and a throttle disable signal. A downstream valid signal is generated by the first pipeline stage based on an upstream valid signal and the delayed ready signal. An upstream ready signal is generated by the first pipeline stage based on the delayed ready signal and the downstream valid signal.
Public/Granted literature
- US20140365750A1 VOLTAGE DROOP REDUCTION BY DELAYED BACK-PROPAGATION OF PIPELINE READY SIGNAL Public/Granted day:2014-12-11
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