Invention Grant
- Patent Title: Double patterning method of forming semiconductor active areas and isolation regions
- Patent Title (中): 形成半导体有源区和隔离区的双重图案化方法
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Application No.: US14162309Application Date: 2014-01-23
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Publication No.: US09293358B2Publication Date: 2016-03-22
- Inventor: Jeng-Wei Yang , Chien-Sheng Su
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/762 ; H01L21/308

Abstract:
A method of forming active areas and isolation regions in a semiconductor substrate using a double patterning process. The method include forming a first material on the substrate surface, forming a second material on the first material, forming a plurality of first trenches into the second material wherein the plurality of first trenches are parallel to each other, forming a second trench into the second material wherein the second trench is perpendicular to and crosses the plurality of first trenches in a central region of the substrate, filling the first and second trenches with a third material, removing the second material to form third trenches in the third material that are parallel to each other and do not extend through the central region of the substrate, and extending the third trenches through the first material and into the substrate.
Public/Granted literature
- US20150206788A1 Double Patterning Method Of Forming Semiconductor Active Areas And Isolation Regions Public/Granted day:2015-07-23
Information query
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